A conventional 3D integration process, also known as chip-stacking, involves stacking and bonding of two or more processed wafers on top of each other and interconnecting the devices of the processed wafers by vias. An existing 3D integration process is schematically illustrated in FIG. 1 wherein three processed wafers 10, 20 and 30, each having a semiconductor device region 12, 22, 32 and an interconnection layer 14, 24, 34, are stacked and bonded to each other via an oxide or nitride bonding layer 16, 26, 36. Different levels of the stack may be connected by vias.
In a sequential or monolithic 3D integration process, the device processing is instead done subsequent to the wafer bonding. An existing sequential 3D integration process is schematically illustrated in FIG. 2 wherein a semiconductor substrate 50 is transferred on top of a wafer 40 having a semiconductor device region 42, an interconnection layer 44, and a bonding layer 46. Processing for forming a semiconductor device region 52 on the front side of the semiconductor substrate 50 is then performed. An interconnection layer 54 may be formed on the semiconductor device region 52. Different levels of the stack may be connected by vias.
3D integration processes allow forming of area efficient chips or integrated circuits. The sequential 3D integration process provides the additional benefit over the conventional integration process of enabling reduced device layer spacing and via height compared to the chip-stacking technique since the wafer 40 supports the substrate 50 during the device processing on the substrate 50 and hence reduces the number of wafers needed. However there is still a need for further improvements in area efficiency.